It is well known to receive a timing signal to an integrated circuit, and then synchronize phase to such a received timing signal. A conventional approach to determine phase of the timing signal is to receive the timing signal to a coarse-grain synchronization circuit having a first range to obtain a general indication of phase of such a timing signal. Output of the coarse-grain synchronization circuit along with the timing signal is provided to a fine-grain synchronization circuit having a second range to obtain a more precise indication of phase of such a timing signal. Though the first range is broader than the second range, the second range has smaller increments than the first range.
A coarse-grain phase detection stage may be implemented with a delay line, which is sometimes referred to as the “main” delay line, and a fine-grain phase detection stage may be implemented with a delay line, which is sometime referred to as the “trim” delay line. Such delay lines may be controlled with or part of a delay-locked loop (“DLL”). Notably, fine-grain phase detection stages not having delay lines may be used, such as a phase-locked loop (“PLL”). Unfortunately, delay lines, even those with incremental steps, tend to consume a significant amount of area and power on an integrated circuit die, and PLLS with sufficient granularity and jitter insensitivity tend to be costly.
Accordingly, it would be desirable to provide fine-grain phase detection overcoming one or more limitations of area, power and cost associated with a separate trim delay line or a PLL.